文中对准连续波雷达信号处理算法进行了多处改进,合理设计多级滤波器抽取比,使A/D采样直流延拓分量影响最小化;通过简单移位及加法运算实现抑制度达80dB以上的高通滤波器;为提高系统抗干扰性,创新性的设计了具有免混频系数特性的双数字下变频方案。基于Xilinx公司XC4VSX55器件,整个设计完成了所有雷达信号处理算法及对外接口控制功能,资源占用情况比传统方案减少30%以上,同时依然保持良好的性能,尤其适合低复杂度小型弹载雷达系统。

In this paper, classical quasi-continuous waveform radar signal algorithm was improved in several aspects. To decrease PRF pattern extension of DC component which was caused by A/D sampling, proper multi-stage filter decimation ratio was designed; based on shifting and adding operation, high-pass filter with more than 80 dB stop-band attenuation was implemented; for better anti-interference ability, dual DDC architecture with non-mixture-coefficient was adopted. In term of these innovations, whole system was implemented on Xilinx XC4VSX55 FPGA, with radar signal processing and interface control logic integrated, saving at least 30% hardware resource. At the same time, processing ability still keeps efficient and ingenious. Presented strategy is much suitable for missile-based mini radar system with low complexity.