[an error occurred while processing this directive] [an error occurred while processing this directive] [an error occurred while processing this directive]
[an error occurred while processing this directive]

弹箭与制导学报 >

2014 , Vol. 34 >Issue 3: 199 - 202

DOI: https://doi.org/10.15892/j.cnki.djzdxb.2014.03.050

相关技术

系统芯片的模块选择算法

  • 杨彩宁 ,
  • 卢莺 ,
  • 郭峰
展开
  • 1 西安近代化学研究所,西安 710065
    2 中国兵器工业第203研究所,西安 710065

杨彩宁(1977-),女,陕西米脂人,工程师,研究方向:化工自控设计。

收稿日期: 2014-02-19

  网络出版日期: 2025-05-30

收起

An Algorithm for Selecting Templates of System on Chip

  • YANG Caining ,
  • LU Ying ,
  • GUO Feng
Expand
  • 1 Xi'an Modern Chemistry Research Institute, Xi'an 710065, China
    2 No. 203 Research Institute of China Ordnance Industries, Xi'an 710065, China

Received date: 2014-02-19

  Online published: 2025-05-30

Fold

摘要

全面地分析了现有文献中的模块选取过程和策略,给出了一个新的模块选取的详细算法。该算法将模块选择问题转化为多目标规划问题,首先选取覆盖主线上的顶点的模块,然后再选取覆盖其余顶点的模块。该算法应用广泛,可以简化设计、缩短设计周期、节省设计成本、提高系统的性能。

关键词： 模块选择; 模块化; 关键路径; 芯片

本文引用格式

杨彩宁 , 卢莺 , 郭峰 . 系统芯片的模块选择算法[J]. 弹箭与制导学报, 2014 , 34(3) : 199 -202 . DOI: 10.15892/j.cnki.djzdxb.2014.03.050

Abstract

Module selection process and strategy of the existing literatures were analyzed, a new detailed algorithm of module selection was presented. The algorithm coreverts module selection to mult-objective programming. It consists of two phases: in the first phase, the modules are selected to cover the critical circuits, and in the second phase, the modules are secected to cover the remaining nodes. The algorithm is widely used. It can simplify design, shorten the period of design, reduce design cost, and improve the performance of system.

Key words： module selection; modularity; critical circuits; chip

[an error occurred while processing this directive]

参考文献

[1]
D Sreenivasa Rao, Fadi J. Kurdahi. On clustering for maximal regularity extraction[J]. IEEE Transactions on Computer-Aided Design, 1993, 12(8):1198-1208.
[2]
M Corazao, M Khalaf, L Guerra, et al. Instruction set mapping for performance optimization[C]//Proceedings of the IEEE/ACM International Conference on Computer-aided Design, 1993:518-521.
[3]
F J Kurdahi, C Ramachandran. Evaluating layout area tradeoffs for high level synthesis applications[J]. IEEE Trans, on VLSI Systems, 1993, 1(1):46-55.
[4]
L Stok. Interconnect optimization for multiprocessor architectures[C]//In Proc. of the IEEE Int'l Conf. on Computer Systems and Software, 1990:461-465.
[5]
Yuanqing Guo, Gerard J M Smit, Hajo Broersma, et al. A graph covering algorithm for a coarse grain reconfigurable system[C]//Conference of Languages, Compilers, and Tools for Embedded Systems(LCTESTO), 2003:199-208.
[6]
Michel A J Rosien, Yuanqing Guo, Gerard J M Smit, et al. Mapping applications to FPGA tile[C]//Proceeding of Design, Automation and Test in Europe, 2003:11126-11127.
[7]
Ryan Kastner, Seda Ogrenci-Memik, Elaheh Bozorgzadeh, et al. Instruction generation for hybrid reconfigurable systems[C]//Proceedings of International Conference on Computer-Aided Design(ICCAD), 2001:127-130.
[8]
Amit Chowdhary, Sudhakar Kale, Phani Saripella, et al. A general approach for regularity extraction in datapath circuits[C]//Proceedings of International Conference on Computer-Aided Design(ICCAD), 1998:332-339.
[9]
Miguel R Corazao, Marwan A Khalaf, Lisa MGuerra, et al. Performance optimization using template mapping for datapath intensive high-level synthesis[J]. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, 1996, 15(8):877-888.
[10]
C M Chu, J M Rabaey. Hardware selection and clustering in the hyper synthesis system[C]//Proc. ED AC, IEEE, Computer Society, 1992:176-198.
[11]
Renu Mehra. Exploiting regularity for low-power design[C]//Proceedings of the 1996 IEEE/ACM International conference on Computer-aided Design, 1997:166-172.
[12]
D S Rao, F J Kurdahi. An approach to scheduling and allocation using regularity extraction[C]//Proc. Conference Design Automation, Event ASIC Design, 1993:557-561.
[13]
Sanghun Park. Performance-driven scheduling with bit-level chaining[C]//Proceedings of the 36th ACM/IEEE Conference on Design Automation, 1999:286-291.
[14]
Jennifer L Wang, Seapahn Megerian, Miodrag Potkonjak. Forward-looking objective functions;Concept&applications in high level synthesis[C]//Proceedings of the 39th Conference on Design Automation, 2002:904-909.
[15]
R Lepere, D Trystram. A new clustering algorithm for scheduling with large communication delays[C]//16th IEEE-ACM Annual International Parallel and Distributed Processing Symposium, IPDPS 02, 2002.
[16]
邦迪J A, 默蒂U S R. 图论及其应用[M]. 吴望明, 译. 北京:科学出版社, 1984.
[17]
Kanwar Jit Singh, Albert R Wang, Robert K Brayton, et al. Timing optimization of combinational logic[C]//Proceedings, ICCAD88, IEEE Computer Society Press, 1978:282-285.
[18]
Srihari Cadambi, Seth Copen Goldstein. Cpr;A configu--ration profiling tool[C]//Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, 1999:104-109.
[19]
M M Halldorsson, J Radhakrishnan. Greed is Good:Approximating independent sets in sparse and bounded-degree graphs[J]. Proc. of ACM Symposium on the Theory of Computing, 1997, 18(1):145-163.
[20]
Piotr Berman, Martin Fürer. Approximating maximum independent set in bounded degree graphs[C]//Proceedings of the 5th Annual ACM-SIAM Symposium on Discrete Algorithms, 1994:365-371.
[21]
Ravi Boppana, Magnus M Halldorsson. Approximating maximum independent sets by excluding subgraphs[J]. BIT Numerical Mathematics, 1992, 32(2):180-196.
Options
文章导航

/

〈 〉

[an error occurred while processing this directive]