基于FPGA的异步 FIFO的设计方案及性能

王齐双; 黄震春; 蒲海峰

doi:10.15892/j.cnki.djzdxb.2014.06.047

2014 , Vol. 34 >Issue 6: 185 - 189

DOI: https://doi.org/10.15892/j.cnki.djzdxb.2014.06.047

摘要

分析了电子电路设计中异步FIFO设计的两个关键性难点:避免亚稳态现象的出现和空满状态的判断。为解决这两个问题,文中提出了四种方案:基于格雷码、基于移位码的、基于状态标志和基于区间地址的设计方案。设计方案均采用VHDL实现,并在FPGA的基础上进行仿真验证。结果显示这四种方案虽性能迥异,相差较大,但都有其独特的优势之处,能较好的完成异步FIFO的功能。

关键词： 异步 FIFO; 亚稳态; 二级同步链; 格雷码; 移位码

本文引用格式

王齐双 , 黄震春 , 蒲海峰 . 基于FPGA的异步 FIFO的设计方案及性能[J]. 弹箭与制导学报, 2014 , 34(6) : 185 -189 . DOI: 10.15892/j.cnki.djzdxb.2014.06.047

Abstract

Asynchronous FIFO has two key difficulties: metastable protection and identification of empty/full state. To solve these two difficulties, four solutions were proposed: the two are based on gray code and shift code, the other two are based on status flag and interval address. These four solutions were implemented with VHDL, and simulated on FPGA. The result shows that these four solutions all have their own advantages and can work well.

Key words： asynchronous FIFO; metastability; two-level synchronized trigger; gray code; shift code

[an error occurred while processing this directive]

参考文献

[1]	Clifford E Cummings Simulation and Synthesis Techniques for Asynchronous FIFO Design[OL]. http://www.docin.com/p-46476833.html.
[2]	William J Dally, John W Poulton. Digital Systems Engineering[M]. Cambridge: Cambridge University, 1998.
[3]	Vijay A. Nebhrajani Asynchronous FIFO Architectures[OL] http://www.docin.com/p_88158123.html.
[4]	汪路元. FPGA设计中的亚稳态及其缓解措施[J]. 电子技术应用, 2012, 38(8): 13-15.
[5]	李冬, 赵志凯. 一种高性能异步 FIFO 的设计与实现[J]. 微电子学与计算机, 2010, 27(8): 145-148.
[6]	刘彬. 异步FIFO的设计与形式化验证[D]. 长沙: 国防科学技术大学, 2011.

Options

文章导航