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相关技术

基于 FPGA 的数据记录器关键技术优化

  • 文丰 ,
  • 刘佳宁 ,
  • 刘东海
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  • 中北大学电子测试技术国家重点实验室,太原 030051

文丰(1977-),男,四川蓬溪人,副教授,博士,研究方向:高冲击测量技术。

收稿日期: 2017-02-13

  网络出版日期: 2025-05-22

基金资助

国家自然科学基金(51225504)

Key Technologies Optimization of Data Recorder Based on FPGA

  • WEN Feng ,
  • LIU Jianing ,
  • LIU Donghai
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  • National Key Laboratory for Electronic Measurement Technology, North University of China, Taiyuan 030051, China

Received date: 2017-02-13

  Online published: 2025-05-22

摘要

针对存储系统中的指令误判和单片FLASH读写速率慢的问题,设计了一种基于FPGA的高可靠、高速数据记录器。该记录器采用4线指令组合校验机制,配合双计数器消抖的防指令误判技术,最大限度保证指令的可靠识别;采用批次检测的方法管理坏块,有效缩短校验时间,同时应用交替双平面交叉写入和流水线编程模式,FLASH写入速度达到29.92MB/s;应用双FIFO交叉缓存,握手读数的机制,有效保证读取速度。经实践验证,该记录器指令判断准确,读写速率快,具有一定的推广价值。

本文引用格式

文丰 , 刘佳宁 , 刘东海 . 基于 FPGA 的数据记录器关键技术优化[J]. 弹箭与制导学报, 2017 , 37(5) : 119 -122 . DOI: 10.15892/j.cnki.djzdxb.2017.05.037

Abstract

According to the problem of misjudgment instruction and slow writing and reading data rates of single-chip FLASH, a high speed and high reliability data recorder based on FPGA was designed. 4-wire combinational instructions verification mechanism, with the dithering elimination technology of double counter was adopted to prevent instruction misjudgment in this recorder; adopting the method of batch testing management invalid block which shortens the time of verification. In consequence the application of alternating bi-planar cross-write pages and pipeline technique, the FLASH achieve the writing speed of 29. 92 MB/s. Reading mechanism of shaking hands with double FIFO cross cache effective guarantee read speed. By the practical test, the recorder has accurate instruction judgment, great write-read speed, the practical application value is great.

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参考文献

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储成群. 基于LVDS 接口的高速数据记录器的设计[D]. 太原: 中北大学, 2011: 41- 45.
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舒文丽, 吴云峰, 赵启义,等. NAND Flash 存储的坏块管理方法. 电子器件, 2011, 34 (5): 580- 583.
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Micron Technology. MT29F64G08AFAAAWP NAND FLASH Datasheet. 2009.
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车艳霞. 基于Flash的高速数据记录装置关键技术研究[D]. 太原: 中北大学, 2012: 12- 44.
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