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[an error occurred while processing this directive]Key Technologies Optimization of Data Recorder Based on FPGA
Received date: 2017-02-13
Online published: 2025-05-22
文丰 , 刘佳宁 , 刘东海 . 基于 FPGA 的数据记录器关键技术优化[J]. 弹箭与制导学报, 2017 , 37(5) : 119 -122 . DOI: 10.15892/j.cnki.djzdxb.2017.05.037
According to the problem of misjudgment instruction and slow writing and reading data rates of single-chip FLASH, a high speed and high reliability data recorder based on FPGA was designed. 4-wire combinational instructions verification mechanism, with the dithering elimination technology of double counter was adopted to prevent instruction misjudgment in this recorder; adopting the method of batch testing management invalid block which shortens the time of verification. In consequence the application of alternating bi-planar cross-write pages and pipeline technique, the FLASH achieve the writing speed of 29. 92 MB/s. Reading mechanism of shaking hands with double FIFO cross cache effective guarantee read speed. By the practical test, the recorder has accurate instruction judgment, great write-read speed, the practical application value is great.
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