在分析二次雷达S模式信号格式以及CRC原理的基础上,针对传统串行编解码器存在效率低的问题,提出了一种改进型的并行编解码器。在MATLAB中完成编解码器输入与输出关系的计算,根据计算结果,使用VerilogHDL语言在FPGA平台上完成了编解码器的设计,并在Modelsim软件中进行仿真验证。仿真结果表明,在短格式信号的编解码中,并行结构可以在一个时钟周期内完成数据的编解码工作,与传统串行编解码器相比,效率提高了56倍。

In order to solve the problem of low efficiency in traditional serial structure, this article proposed an improved parallel structure based on the analysis of signal format of Mode S for secondary surveillance radar and the principle of CRC. The relationship between input and output of codec is analyzed in MATLAB, according to the result, using Verilog HDL language to accomplish the design of new structure on the FPGA platform, and carries out the simulation in the Modelsim software. The simulation results show that, new structure can realize data encoding and decoding in one clock cycle, the efficiency can improve 56 times comparing to the traditional serial structures in the encoding and decoding of short format signal.