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弹箭与制导学报 >

2017 , Vol. 37 >Issue 5: 19 - 24

DOI: https://doi.org/10.15892/j.cnki.djzdxb.2017.05.005

导弹与制导技术

一种弹载数据链载波同步数字锁相环设计

  • 王鹏 ,
  • 龚克 ,
  • 郭玉霞
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  • 1 信阳师范学院, 河南信阳 464000
    2 中国空空导弹研究院, 河南洛阳 471009

王鹏(1985-),男,河南太康人,高级工程师,博士,研究方向:雷达信号处理、VLSI芯片设计。

收稿日期: 2016-10-30

  网络出版日期: 2025-05-22

基金资助

国家自然科学基金(61571386);河南省科技攻关计划(172102210455);信阳师范学院青年骨干教师资助计划

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Carrier Synchronizing Digital PLL Design for Missile-borne Data Link System

  • WANG Peng ,
  • GONG Ke ,
  • GUO Yuxia
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  • 1 Xinyang Normal University, Henan Xinyang 464000, China
    2 China Airborne Missile Academy, Henan Luoyang 471009, China

Received date: 2016-10-30

  Online published: 2025-05-22

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摘要

针对模拟锁相环稳定性差、参数调节困难的缺陷,利用双线性变换建立了模拟锁相环与数字锁相环设计参数的严格对应关系。采用现场可编程门阵列完成了基于软件定义无线电理念的全数字化Costas环设计及实现,在片内集成Microblaze软核以实现环路锁定频率及捕捉带性能的动态调整,环路收敛特性优异,经布局布线后静态时序工具报告最高工作频率可达466MHz。设计通用性较强,可推广至各类软件无线电硬件平台开发。

关键词： 数据链; 锁相环; 环路滤波; 双线性变换; 软件定义无线电

本文引用格式

王鹏 , 龚克 , 郭玉霞 . 一种弹载数据链载波同步数字锁相环设计[J]. 弹箭与制导学报, 2017 , 37(5) : 19 -24 . DOI: 10.15892/j.cnki.djzdxb.2017.05.005

Abstract

To improve traditional analog PLL's performance and stability, based on bilinear transformation, relationships between analog-domain and digital-domain design parameters were established strictly. A full-digitalized Costas loop was implemented on FPGA based on software defined radio technology, Microblaze soft core CPU was also instanced to modify loop lock frequency and capture band parameter dynamically. Convergence property was proved to be marvelous, and the maximum work frequency of routed design can attain 466 MHz. Presented design can be used for general SDR development because of highly-parameterized character.

Key words： data link; PLL; loop filter; bilinear transform; software defined radio

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