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Journal of Projectiles, Rockets, Missiles and Guidance >

2014 , Vol. 34 >Issue 6: 185 - 189

DOI: https://doi.org/10.15892/j.cnki.djzdxb.2014.06.047

CORRELATION TECHNOLOGY

Designs and Performance Study for Asynchronous FIFO Based on FPGA

  • WANG Qishuang ,
  • HUANG Zhenchun ,
  • PU Haifeng
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  • 1 Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
    2 No. 203 Recearch Institute of China Ordnance Industries, Xi'an 710065, China

Received date: 2014-01-01

  Online published: 2025-05-30

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Abstract

Asynchronous FIFO has two key difficulties: metastable protection and identification of empty/full state. To solve these two difficulties, four solutions were proposed: the two are based on gray code and shift code, the other two are based on status flag and interval address. These four solutions were implemented with VHDL, and simulated on FPGA. The result shows that these four solutions all have their own advantages and can work well.

Key words： asynchronous FIFO; metastability; two-level synchronized trigger; gray code; shift code

Cite this article

WANG Qishuang , HUANG Zhenchun , PU Haifeng . Designs and Performance Study for Asynchronous FIFO Based on FPGA[J]. Journal of Projectiles, Rockets, Missiles and Guidance, 2014 , 34(6) : 185 -189 . DOI: 10.15892/j.cnki.djzdxb.2014.06.047

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