In order to solve the problem of low efficiency in traditional serial structure, this article proposed an improved parallel structure based on the analysis of signal format of Mode S for secondary surveillance radar and the principle of CRC. The relationship between input and output of codec is analyzed in MATLAB, according to the result, using Verilog HDL language to accomplish the design of new structure on the FPGA platform, and carries out the simulation in the Modelsim software. The simulation results show that, new structure can realize data encoding and decoding in one clock cycle, the efficiency can improve 56 times comparing to the traditional serial structures in the encoding and decoding of short format signal.