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Journal of Projectiles, Rockets, Missiles and Guidance >
Carrier Synchronizing Digital PLL Design for Missile-borne Data Link System
Received date: 2016-10-30
Online published: 2025-05-22
To improve traditional analog PLL's performance and stability, based on bilinear transformation, relationships between analog-domain and digital-domain design parameters were established strictly. A full-digitalized Costas loop was implemented on FPGA based on software defined radio technology, Microblaze soft core CPU was also instanced to modify loop lock frequency and capture band parameter dynamically. Convergence property was proved to be marvelous, and the maximum work frequency of routed design can attain 466 MHz. Presented design can be used for general SDR development because of highly-parameterized character.
Key words： data link; PLL; loop filter; bilinear transform; software defined radio
WANG Peng , GONG Ke , GUO Yuxia . Carrier Synchronizing Digital PLL Design for Missile-borne Data Link System[J]. Journal of Projectiles, Rockets, Missiles and Guidance, 2017 , 37(5) : 19 -24 . DOI: 10.15892/j.cnki.djzdxb.2017.05.005
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