In spaceborne synthetic aperture radar (SAR), in allusion to the requirement of testing time sequence in data transmission subsystem, a new design of SAR load simulator system is implemented, which is based on FPGA. The system adopts FPGA as basic to build data processing unit, which is used to implement mass SAR simulation data storage, sequence synthesis of clock-data and BIT function. The man-machine and LVDS output interface are also implemented by communication unit and LVDS output unit. To meet the test requirements of timing perturbation injection in data transmission subsystem, the delay unit based on IODELAY primitive, is designed by timing rules. Finally, the performance and robustness are assessed through the simulation and test, and the results show that the range of timing perturbation is from 8ns to 8ns with 1ns step, when delay unit is working in SAR load simulator system.