In this paper, classical quasi-continuous waveform radar signal algorithm was improved in several aspects. To decrease PRF pattern extension of DC component which was caused by A/D sampling, proper multi-stage filter decimation ratio was designed; based on shifting and adding operation, high-pass filter with more than 80 dB stop-band attenuation was implemented; for better anti-interference ability, dual DDC architecture with non-mixture-coefficient was adopted. In term of these innovations, whole system was implemented on Xilinx XC4VSX55 FPGA, with radar signal processing and interface control logic integrated, saving at least 30% hardware resource. At the same time, processing ability still keeps efficient and ingenious. Presented strategy is much suitable for missile-based mini radar system with low complexity.